Due to the advancement in the network transmission technology and the demands in the installed base of the computer networks, the network data transmission rate in hardware environment has been increased. Therefore, it becomes more and more important to correctly recover data (clock signal).
Nowadays, a phase-locked loop is often utilized to recover data. During the data recovery process, usually the received data can be correctly recovered (read) by using a phase detector to synchronize the recovering clock and the received data at the receiving end. In other words, the phase detector plays a very important role in whether the data can be correctly recovered by a phase-locked loop.
As mentioned above, FIG. 1 illustrates a prior art phase-locked loop 1 for data recovery comprising a phase detector 11, a charge pump 12, a loop filter 13, and a voltage controlled oscillator 14. The phase detector 11 is used to receive a data (clock) signal from outside and a feedback clock signal CK.sub.vco from the voltage controlled oscillator 14. The phase detector 11 compares the two received signals, outputs a control signal up or dn according to the phase difference .theta..sub.e of the two received signals (.theta..sub.e =.theta..sub.data -.theta..sub.clock). The control signal up or dn is used to control the charge pump 12. As shown in FIG. 2(a), when the transition edge of the data (clock) signal data leads the falling edge of the feedback clock signal CK.sub.vco, the phase detector 11 outputs an up signal. On the other hand, as shown in FIG. 2(b), when the transition edge of the data (clock) signal data lags behind the falling edge of the feedback clock signal CK.sub.vco, the phase detector 11 outputs a dn signal. The up and dn control signals outputted from the phase detector 11 control the charge/discharge operation of the charge pump 12. A voltage signal Vd is generated by the charge pump 12 according to the up and dn control signals. The loop filter 13 generates a voltage Vc for controlling the voltage-controlled oscillator 14. In accordance with the above-mentioned voltage Vc, the voltage-controlled oscillator 14 outputs a clock signal CK.sub.vco which is applied to the phase detector 11.
Referring to FIG. 3, the phase detector 11 of the phase-locked loop 1 is constituted by four flip-flops 111, 112, 113, 114, and two OR gates 115, 116. The flip-flops 111 and 112 receive the inverted data signal data from outside as well as the data itself, respectively. The clock signal CK.sub.vco from the voltage-controlled oscillator 14 is applied to the complementary reset terminals rb of the flip-flops 111 and 112 so as to output control signals up1 and up2, respectively. The flip-flops 113 and 114 are utilized to receive the complementary data signal data from outside and the data itself. The inverted signal of CK.sub.vco is applied to the complementary reset terminals rb of the flip-flops 113 and 114 so as to output control signals dn1 and dn2, respectively. According to the control signals up1 and up2, the OR gate 115 generates a control signal up (refer to FIG. 2(a)) for controlling the charge pump 12. Similarly, according to the control signals dn1 and dn2, the OR gate 116 generates a control signal dn (as shown in FIG. 2(b)) to control the charge pump 12.
Referring to FIG. 1, the voltage Vd is controlled by the two received signals (up, dn) of the charge pump 12. In other words, the variation of the control voltage Vd is related with the phase error .theta..sub.e. FIG. 4 illustrates the relation between the variation of the voltage Vd and the phase error .theta..sub.e. As shown in FIG. 4, when the data signal data has a phase lagging behind the clock signal CK.sub.vco, the smaller the phase error .theta..sub.e is, the more the voltage Vd varies, which is contrary to our prediction. Theoretically, the phase error .theta..sub.e is supposed to approximate to zero and closely moves around the origin when a phase-locked loop nearly enter a phase-locked state. However, according to the above description, when the data signal data of a phase-locked loop has a phase lagging behind the clock signal CK.sub.vco, a rapid variation of the voltage Vd will be generated, which induces clock jitter. Tolerance for data random jitter thus become worse. In other words, it is impossible to reduce the clock jitter utilizing the conventional phase detector 11, tolerance for data random jitter is thus hardly improved.